Although semiconductor processing technology continues to advance, integrated circuits often include manufacturing errors. While the integrated circuits are still part of the production wafer, it is common to perform testing on the wafer to identify individual integrated circuits that do not perform properly. When the wafer is subsequently diced to produce individual integrated circuit die, each singulated die having an integrated circuit that failed to pass the testing can be segregated from the production. The singulated dice with integrated circuits that passed testing are forwarded on for further processing (such as, for example, packaging). The segregated dice having integrated circuits that failed testing may be discarded and may also be subjected to further testing to try to identify the precise circuitry that caused the testing failure.
To assist with the testing process on the wafer, it is common for each integrated circuit to include specifically designed test circuitry. Access to this test circuitry is made using automated test equipment (ATE) that probes the integrated circuit through probe pads that are electrically connected to the test circuitry. Voltages may be applied to certain probe pads, control signals may be applied to other probe pads and test output signals may be obtained from yet other probe pads.
One aspect of testing of particular importance evaluates operation of the integrated circuit at extreme operating conditions. For example, at extremes associated with temperature (high and low temperatures) and extremes of supply voltage (high and low voltage). The integrated circuits must pass testing at these extremes in order to proceed on for further processing.
FIG. 1 shows a simplified block diagram of a power management circuit 10 of an integrated circuit. The power management circuit 10 includes a plurality of functional voltage monitors (FVM) 16. These functional voltage monitors 16 are each associated with a certain power supply node 18. For example, the power supply node may be a relatively higher supply voltage (HV) node, a relatively lower supply voltage (LV) node or a (middle) supply voltage (MV) node for a voltage therebetween. The power supply nodes may be connected to a pad of the integrated circuit or may be connected to the output of a power supply circuit (such as a voltage regulator) contained within the integrated circuit. Each functional voltage monitor 16 operates to compare the voltage at the associated power supply node 18 to a voltage threshold. In the event that the monitored power supply voltage crosses (for example, falls below) the voltage threshold, the functional voltage monitor 16 asserts a reset signal 20. The reset signal 20 in the context of undervoltage monitoring is typically of the power on reset (POR) type which causes functional circuits 24 of the integrated circuit to reset their operation.
Although FIG. 1 illustrates a single HV functional voltage monitor 16, it will be understood that the power management circuit 10 may include a plurality of functional voltage monitors related to high voltage monitoring over a range of voltages (such as, for example, over a range from 2.7V to 6V with specific ones of the plurality of included HV voltage monitors being associated with different thresholds such as 2.7V, 3.0V, . . . , 6V). Likewise, the MV functional voltage monitor is representative of a plurality of functional voltage monitors related to medium voltage monitoring over a range of voltages (such as, for example, over a range from 1.5V to 2.16V with specific ones of the plurality of MV voltage monitors being associated with different thresholds such as 1.5V, . . . , 2.16V). Still further, the LV functional voltage monitor is representative of a plurality of functional voltage monitors related to low voltage monitoring over a range of voltages (such as, for example, over a range from 0.65V to 1.15V with specific ones of the plurality of LV voltage monitors being associated with different thresholds such as 0.65, . . . , 1.15V).
During integrated circuit testing, and in particular in association with the testing of the integrated circuit at extremes of supply voltage and temperature, the automated test equipment may apply certain voltages to the power supply nodes 18. As a result of the applied extreme operating condition test, the voltage at a given one of the power supply nodes 18 monitored by the functional voltage monitors 16 could fall below the test threshold and cause the reset (by POR) of the functional circuits 24. In some circumstances, this is undesirable because testing must then wait for the functional circuits to reset before moving on to a next test, thus delaying completion of test processing. To address the foregoing concern, it is known in the art to mask the reset signal 20 during testing. Masking circuitry 30, such as a logic gate circuit, responsive to a test mode signal 32 is accordingly provided between the output of the functional voltage monitors 16 and the functional circuits 24. When the test mode signal 32 is asserted, the masking circuitry 30 blocks the reset signal 20 from propagating to the functional circuits 24 and causing their reset.